Many modern electronic devices operate with one or more inputs as analog (continuously variable) signals. Since it is becoming more common for these devices to be digital in nature, it is necessary at some point to convert the analog signal to a sampled digital signal. A key part of this analog to digital conversion process is a sample and hold circuit.
The sample and hold circuit is placed ahead of the circuit element or elements that do the actual conversion to digital values. Because the conversion takes a finite amount of time, it is necessary to provide the converter circuit with a stable, fixed, signal for the duration of the sampling time. The sample and hold circuit is the element that performs this operation. The sample and hold circuit consists of some sort of element that can sample the input signal for a short period of time, corresponding to the conversion time, and then provide this sampled value to the actual converter circuitry. The sample and hold may simply take a brief sample of the input signal or it may average the input signal over the sampling interval.
FIG. 1 shows a conventional sample-and-hold architecture, referred to as a single-sampling architecture. The circuit comprises a buffer amplifier 102 that serves to buffer the input signal, a sampling capacitor 104, an output amplifier 106, and three switches (108, 110, and 112). The switches (108, 110, and 112) are controlled by a series of clock signals (120, 122, 124, and 126), shown in FIG. 2. For ease of understanding, a clock signal (122, 124, and 126) has been associated with each switch of FIG. 1. The switches (108, 110, and 112) operate so that the switches (108, 110, and 112) are closed whenever the associated clock signal is high and are opened when the associated clock signal is low.
In the first half cycle of the main clock signal 120, switch 110 is opened when clock signal q2 goes low. Switches 108 and 112 are then closed as clock q1 and q1p go high. Therefore, the capacitor C is connected to the output of buffer 102 and will charge to the voltage of the output of buffer 102 (tracking mode). At the end of the tracking mode, switch 112 is opened when clock signal q1p goes low, and then switch 108 is opened when clock signal q1 goes low. Finally switch 110 is closed when clock signal q2 goes high, placing the capacitor C in a feedback path between the output of amplifier 106 and the input of amplifier 106. This will cause the output of the amplifier 106 to swing to the voltage of the capacitor C. This voltage is held at the amplifier 106 output for half cycle of the main clock signal (hold mode).
The sample and hold output provides samples of the output of buffer 102 every clock cycle (Tmclk). However, due to the lack of overlapping between tracking and hold modes, the buffer 102 and the sample and hold outputs have only half a clock cycle (Tmclk/2) to settle. The buffer 102 and the sample and hold outputs are idle in the other half clock cycle.
A shorter available settling time requires a higher power consumption to achieve a given distortion level. This is because the time it takes a capacitor to charge to the buffer voltage is dependent on the current capacity of the buffer amplifier. Similarly, the time it takes the output amplifier to charge up to the voltage held on the capacitor is dependent on the current capacity of the output amplifier. The higher the current capacity, the more power the amplifiers consume. In order to achieve high accuracy in the tracking of the output of the amplifier to the input, shorter settling times are desirable. Therefore, the idle times of one half of a clock signal cycle in each of the tracking and hold modes require higher power consumption.
It would therefore be desirable to provide an alternative sample and hold architecture that utilized idle times and lowered the requirement for power consumption in the buffer and output amplifiers.
A first aspect of the present invention is a sample and hold circuit. The sample and hold circuit includes a buffer to receive an input signal to be sampled; an amplifier to output the sampled signal; a first sampling capacitor operatively connected between the buffer and the amplifier; a second sampling capacitor operatively connected between the buffer and the amplifier; a first set of switches to connect the first sampling capacitor to an output of the buffer during a positive phase of a clock and to connect the first sampling capacitor across a feedback path of an amplifier during a zero phase of the clock; and a second set of switches to connect the second sampling capacitor to the output of the buffer during the zero phase of the clock and to connect the second sampling capacitor across the feedback path of the amplifier during the positive phase of the clock.